Altera SDC and TimeQuest API - Manual (Page 19)

Chapter 2: SDC and TimeQuest API Package and Commands 2–9
sdc
© December 2009 Altera Corporation SDC and TimeQuest API Reference Manual
Clock generation can also be specified with the -edges and -edge_shift options. The -edges option accepts a
list of three numbers specifying the master clock edges to use for the first rising edge, the next falling edge,
and next rising edge. Edges of the master clock are labeled according to the first rising edge (1), next falling
edge (2), next rising edge (3), etc. For example, a basic clock divider can be specified equivalently with
-divide_by 2 or -edges {1 3 5}. The -edge_shift option accepts a list of three time values, the amount to shift
each of the three edges.
The value of the targets is either a collection or a Tcl list of wildcards used to create a collection of the
appropriate type. The values used must follow standard Tcl or TimeQuest-extension substitution rules.
See the help for use_timequest_style_escaping for details.
Example
# Create a clock and a divide-by-2 generated clock
create_clock -period 10 [get_ports clk]
create_generated_clock -divide_by 2 -source [get_ports clk] -name clkdiv \
[get_registers clkdiv]
# An equivalent generated clock
create_generated_clock -edges {1 3 5} -source [get_ports clk] -name \
clkdiv [get_registers clkdiv]
# Specify a clock multipler with a 60% duty cycle
create_generated_clock -multiply_by 2 -duty_cycle 60 \
[get_pins clkmult|combout]
# Specify an inverted divide-by-2 clock relative to the output of the
# source clock
create_generated_clock -divide_by 2 -invert -source [get_ports clk] -name \
nclkdiv [get_registers clkdiv]
# Specify a divide-by-2 clock with a 90-degree phase shift
create_generated_clock -divide_by 2 -phase 90 -source [get_ports clk] \
-name clkdiv [get_registers clkdiv]
# Assign two clocks to an input port that are switched externally,
# along with an internal clock divider.
create_clock -period 10 -name clk100Mhz [get_ports clk]
create_clock -period 6.667 -name clk150Mhz -add [get_ports clk]
create_generated_clock -divide_by 2 -name clk50Mhz -source [get_ports \
clk] -master_clock clk100Mhz -add [get_registers clkdiv]
create_generated_clock -divide_by 2 -name clk75Mhz -source [get_ports \
clk] -master_clock clk150Mhz -add [get_registers clkdiv]