Altera Cyclone II EP2C35 PCI Development Board - Manual (Page 7)

Altera Corporation Core Version a.b.c variable 1–1
May 2005 Preliminary
1. Introduction
General
Description The Cyclone ™ II EP2C35 PCI Development Board provides a hardware
platform for developing and prototyping high-speed PCI and PCI-X bus
interfaces, double data rate 2 (DDR2) SDRAM, and the 10/100 Ethernet
interface.
Based on Cyclone II FPGAs and using Altera ® MegaCore ® functions or
Altera Megafunction Partners Program (AMPP SM ) megafunctions, the
Cyclone II EP2C35 PCI Development Board allows users to quickly solve
design problems that typically require time-consuming, custom
solutions.
The board supports the EP2C35F672 Cyclone II device, which is
optimized for high-bandwidth DSP functions. The board also supports
the PCI Local Bus Specification, Revision 3.0 and PCI-X, Revision 2.0 mode 1.
Altera provides a DDR2 SDRAM reference design for use as either a
design starting point or an experimental platform. The reference design is
designed and tested by Altera engineers and distributed with the PCI
Development Kit, Cyclone II Edition (ordering code: PCI-DEVKIT-2C35).
f
For more information on the DDR2 SDRAM reference design, refer to
AN 390: PCI-to-DDR2 SDRAM Reference Design.
Components
The board provides the following components:
■ Short-form universal PCI (3.3 or 5.0 V) card
● 32 or 64-bit PCI bus operating at 33 or 66 MHz
● 32 or 64-bit PCI-X bus operating at 66 or 100 MHz
■ Memory
● Two 32-MByte DDR2 SDRAM devices
● EPCS64 devices
■ FPGA device configuration
● Switch-selectable on power-up, choose one of two serial
configuration devices (EPCS64 devices). One device contains
the pre-loaded factory default design, and the other device is for
user-programming. Configuration data is downloaded via the
USB-Blaster
™ download cable.
■ Flexible clocking options
● Socketed 100-MHz high-speed clock oscillator
● SMA connector clock input