Altera Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board - Manual (Page 10)

1–4 Reference Manual Altera Corporation
Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006
Handling the Board
■ Clocking evaluation to qualify the Stratix II GX device with user
clock sources
■ Demonstrate signal integrity features on a standalone basis
Data Rate & Clock Frequency Support Per Protocol
Table 1–1 shows the board’s data rate and clock frequency support per
protocol.
Handling the
Board When handling the board, it is important to observe the following
precaution:
w
Static Discharge Precaution—Without proper anti-static
handling, the board can be damaged. Therefore, use anti-static
handling precautions when touching the board.
Table 1–1. Board Protocol Support
Protocol
Data Rate
(Gbps)
Clock
Frequency
(MHz)
Clock Source
6G - CEI 6.25 156.25 On board oscillator
5G scrambled 5 156.25 On board oscillator
4G FC, (1) 4.25 – SMA clock input
XAUI 3.125 156.25 On board oscillator
PCI-Express/PIPE 2.5 100 On board oscillator
SONET backplane 2.488 – SMA clock input
2G FC, (1) 2.125 – SMA clock input
HD - SDI 1.485 – SMA clock input
GIGE 1.25 125 On board oscillator
1G FC, (1) 1.063 – SMA clock input
Note to Table 1–1 :
(1) There is no support planned for Fibre channel protocol. This table only shows
supported data rate.