Altera Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board - Manual (Page 7)

Altera Corporation Reference Manual 1–1
May 2006 Preliminary
1. Introduction
General
Description The Stratix ® II GX EP2SGX90 transceiver signal integrity development
board provides a hardware platform for developing and prototyping
high-speed designs using power-efficient Stratix II GX devices. The
transceiver technology embedded in Stratix II GX devices ensures that
signal integrity extends to high frequencies while also providing a
power-efficient, single-chip solution that supports the following
high-speed serial protocols:
■ PCI-Express
■ CEI-6G
■ Gigabit Ethernet
■ XAUI
■ Serial RapidIO ™
■ SONET Backplane
■ SDI
■ SerialLite II
As board designs move into the Gbps space, it is increasingly more
difficult to maintain signal integrity. In fact, increasing data rates for both
I/O interfaces and memory interfaces can present significant data
transmission problems and performance issues.
The Stratix II GX device’s embedded transceivers provide enhanced
transmit pre-emphasis technology that conditions the signal prior to
transmission as well as programmable receiver equalization circuitry.
Also, because the Stratix II GX device’s embedded transceivers have
built-in clock data recovery, you do not have to route the clock and data
on the board, which greatly simplifies high-speed board designs.
To further simplify the process, Altera ® provides a reference design for
use as either a design starting point or an experimental platform. The
reference design is designed and tested by Altera engineers and
distributed with the Transceiver SI Development Kit, Stratix II GX
Edition (ordering code: DK-SI-2SGX90N).