Altera Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board - Manual (Page 3)

Altera Corporation iii
May 2006 Preliminary
Contents
About this Manual
Revision History ......................................................................................................................................... v
How to Contact Altera ............................................................................................................................... v
Typographic Conventions....................................................................................................................... vi
Chapter 1. Introduction
General Description................................................................................................................................ 1-1
Board Component Blocks................................................................................................................. 1-2
Block Diagram ................................................................................................................................... 1-3
Target Applications........................................................................................................................... 1-3
Data Rate & Clock Frequency Support Per Protocol ................................................................... 1-4
Handling the Board ................................................................................................................................ 1-4
Chapter 2. Board Components & Interfaces
Board Overview ...................................................................................................................................... 2-1
Featured Device ...................................................................................................................................... 2-6
Clocking Circuitry ................................................................................................................................. 2-7
Clock Buffer Functional Descriptions ............................................................................................ 2-9
ICS557-03 (U5): Spread Spectrum Clock Generator for PCI-Express ................................. 2-10
ICS8543 (U8): General Purpose 1:4 Differential Fanout Buffer ........................................... 2-11
ICS83023 (U7): Differential I/O to Single Converter for Trigger Clock ............................ 2-11
Interfaces ................................................................................................................................................ 2-12
SMA Connectors for High-Speed I/O ............................................................................................... 2-12
USB Interface ......................................................................................................................................... 2-14
General User Interfaces ........................................................................................................................ 2-16
Debug Header (J1) ........................................................................................................................... 2-16
LEDs (D1 Through D8) ................................................................................................................... 2-18
7-Segment Displays (D9, D10) ....................................................................................................... 2-19
Push-Button Switches (S1 Through S6) ........................................................................................ 2-21
DIP Switches (S7 and S8) ................................................................................................................ 2-22
Clock Selection Switches (S9 and S10) ......................................................................................... 2-24
Power Supply ....................................................................................................................................... 2-25
Thermal Management Block ............................................................................................................... 2-27
FPGA Configuration Block ................................................................................................................. 2-28
JTAG Configuration ........................................................................................................................ 2-28
Active Serial Configuration Using EPCS64 Device (U22) ......................................................... 2-28
Flash Memory ....................................................................................................................................... 2-30