Altera Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board - Manual (Page 34)

2–24 Reference Manual Altera Corporation
Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006
Interfaces
Table 2–16 lists the spread spectrum output selection DIP switch settings.
Table 2–17 lists PCIe clock and quad transceiver clock DIP switch
settings.
1 Switches 7 and 8 are not connected.
Clock Selection Switches (S9 and S10)
Switch S9 is used to control whether the clock input is driven from an
external or an on-board source. Switch S10 is used to apply power to the
board. The positions for these switches are labelled on the silk-screen.
Table 2–18 lists clock selection switch settings for board reference S9.
Table 2–16. Spread Spectrum Output Selection Setting (S8)
Switch Center =/-0.25 Down -0.5 Down -0.75 No Spread
SW3 Closed Open Closed Open
SW4 Closed Closed Open Open
Table 2–17. PCIe Clock & Quad Transceiver Clock DIP Switch Settings (S8)
PCIe Clock DIP Switch Setting Quad Transceiver Clock DIP Switch Setting
Switch Enable Clock Disable Clock Switch Enable Clock Disable Clock
SW5 Open Closed SW6 Open Closed
Table 2–18. Clock Selection Switch (S9)
Switch Setting Result
Switch in OSC setting Selects the 156.25-MHz oscillator
Switch in SMA position Selects external clock input