Altera Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board - Manual (Page 14)

2–4 Reference Manual Altera Corporation
Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006
Board Overview
Table 2–1 describes the components and lists their corresponding board
references.
Table 2–1. Stratix II GX Transceiver SI Development Board Components & Interfaces (Part 1 of 3)
Type
Component/
Interface
Board
Reference
Description Page
Featured
Device
FPGA Stratix II GX
device U20 EP2SGX90EF1152C3NES or EP2SGX90EF35C3NES 2–6
User
Interfaces
I/O Push-button
switches S1-S6 Six push-button switches for user-defined, logic inputs. 2–21
I/O DIP switch S7 Eight toggle DIP switches for user-defined, logic inputs. 2–22
I/O LEDs D1-D8 Eight user-defined LEDs 2–18
I/O Dual seven-
segment
display D9, D10 Dual seven-segment display 2–19
I/O Slide switch S9 Double-pole, single-throw slide switch for selecting
between the 156.25 MHZ oscillator and the SMA external
clock inputs to supply the clocks to the three quad
transceivers. 2–24
I/O DIP switch S8 Eight toggle DIP switches for selecting PCIe clock speed,
PCIe clock spread-spectrum setting, and the output enable
of the clocks to the three quad transceivers. 2–22
Debugging Interfaces
I/O Debug header J1 A twenty-pin connector that is connected to 20 general I/Os
on the FPGA. 2–16
Connections & Interfaces
I/O USB UART U2, J2 USB interface to the Stratix II GX device for device
configuration and communication with applications running
on the device. 2–14
I/O SMA transmit
and receive
connectors J26-J49 SMA connectors with the transmit and receive signals from
the quad transceivers 2–12
Configuration & Reset
Input Connector J23 Header for programming the EPCS64 serial configuration
device. 2–28
Input Connector J24 Header for configuring the Stratix II GX device. 2–28
Input Jumper
header J25 Jumper header to select which JTAG source the board
uses, i.e., the JTAG header configuration or the USB JTAG
configuration. 2–28