Altera Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board - Manual (Page 17)

Altera Corporation Reference Manual 2–7
May 2006 Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board
Board Components & Interfaces
You can configure the Stratix II GX device in one of two ways:
■ Active serial configuration via the EPCS64 device
■ JTAG configuration
Clocking
Circuitry The Stratix II GX transceiver signal integrity development board’s
clocking circuitry is designed to be flexible and easy to use. In fact, with
the Stratix II GX device’s embedded transceivers, you do not need to
route the board’s clock and data signals. Instead, the embedded
transceivers route the clock and data signals to the appropriate
destination.
The Stratix II GX devices have dedicated phase-locked loops (PLLs) for
high-speed transceivers, enhanced PLLs for spread-spectrum and general
purpose clocking, and fast PLLs for high-speed differential I/O clocking,
which support the high-speed interfaces described in this chapter. See
Figure 2–3 .
The clocking block is comprised of:
■ High-speed clock oscillators:
• 156.25-MHz oscillator
• 50-MHz oscillator
■ 25 MHz crystal
■ SMA connectors for clocking input and output signals
Table 2–3 lists the board’s clocking parts list.
Table 2–3. Clocking Block Parts List
Part Name
Number of
Units
Board
Reference
Purpose
ICS557-03 1 U5 Spread spectrum PLL
ICS8543 1 U8 Clock buffer to input
multiplexer to 4 LVDS outputs
ICS830231 1 U7 Clock buffer differential to
single-ended converter
SMA connectors 12 J3 - J14 High-speed interface support
25-MHz crystal 1 U6 Supports the ICS557-03 clock
buffer
156.25-MHz oscillator 1 U9 Supports the OIF, CEI-6G, and
XAUI protocols
50-MHz oscillator 1 U10 Supports the ICS8543 clock
buffer