Altera Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board - Manual (Page 19)

Altera Corporation Reference Manual 2–9
May 2006 Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board
Board Components & Interfaces
Figure 2–3 shows the clock signals passing through logic translators and
automatically routing to the appropriate destination.
Figure 2–3. Clocking Circuitry Automatic Routing Paths
Clock Buffer Functional Descriptions
This section provides functional descriptions for the board’s three clock
buffers:
■ ICS557-03 (U5)
■ ICS8543 (U8)
■ ICS83023 (U7)
ICS557-03
ICS 8 3023
refclk1 in Q u ad1
refclk0 in Q u ad2
PCI-Express Trigger Clock (J3)
refclk1 in Q u ad2
refclk1 in Q u ad3
refclk0 in Q u ad1
refclk0 in Q u ad3
Glo b al Clock for FPGA Block
Glo b al Clock for FPGA Block
General Purpose
Clocking Buffer:
2:1 Multiplexer
to a 1:4 LVDS
Fanout
Buffer (U8)
Spread Spectrum
Clock Generator for PCI-Express (U5)
ICS 8 543
50 MHz
Oscillator
Output Clock
from FPGA Side
(P = J11, N = J13)
SMA Connector Clock
Input (P = J5, N = J6)
Differential I/O to
LVCMOS Translator (U7)
SMA
Connector
Clock Input
(P= J12, N = J14)
156 MHz
Oscillator
25 MHz
Oscillator
= L V PECL/L V DS Inp u t
= HCSL O u tp u t
= L V DS O u tp u t
Basic Trigger Clock (J4)
(P = J7, N = J 8 )
(P = J9, N = J10)