Epson Epson - Manual (Page 165)

Cache
8 or 16KB of internal cache in the
processor; supports 128, 256, or 512KB of
external cache with 32K x 8,64K x 8, or
128K x 8, 15ns or 20ns SRAM DIP chips
and a 32K x 8 tag chip
Math
coprocessor
Math coprocessor built into the processor
on all DX and Intel Pentium OverDrive
processors
Clock/
calendar
Real-time clock, calendar, and CMOS
RAM socketed on main system board with
integrated Lithium battery
Controllers
PCI Chipset
Provides PCI caching, memory and
control for the PCI bus, and the
two-channel PCI IDE interface; integrated
PCI bridge translates CPU bus cycles to
PCI bus cycles and CPU-to-PCI memory
write cycles to PCI burst cycles
Video
Diskette
Cirrus Logic@ GD5430 high-performance
GUI accelerator controller supports
resolutions up to 1024 x 768 in 256 colors
with 1MB of VRAM; 1280 x 1024 with 2MB
of VRAM
Controller on main system board supports
up to two diskette drives or one diskette/
combo diskette and one tape drive
Specifications A-3