Epson Multi-mode Data Controller MFJ-1278B - Manual (Page 305)

MFJ-1278B MULTI-MODE HARDWARE
Other integrated circuits are used for functions including clock oscillator, baud-rate
generator, memory-space decoder, power supply and voltage inverter, clock recovery,
transmit watch-dog timer and modem. Refer to the schematic diagram while reading the
following circuit descriptions.
DETAILED CIRCUIT DESCRIPTION
Oscillator
Components U10a, U10b, U10c, R46, R47, R48, C24, C47, C51, and crystal Y1 provide an
accurate crystal-controlled oscillator for system timing.
Resistor R48 forces inverter U10a into its linear region and provides a load for crystal Y1.
Capacitor C47 provides an adjustable reactive element to allow the oscillator's frequency to
be precisely set (this precision is not normally required). Inverter U10c buffers the clock for
additional stability before driving additional dividers.
Resistor R46 is used to bias "HCT" logic to the proper levels for best oscillator operation; it
is not necessary if U10 is an "HC" logic element.
Dividers and Baud-rate Generator
Components U10e, U10f, U4a, U4b, U1, U30 and U31 provide clock outputs derived from
the oscillator. Electronics switches within U30 and U31 provide all the terminal and RF baud
rate signals under software command.
Inverter U10f provides buffering and isolation between the divide-by-two output of counter
U4a and the capacitive load presented by the CPU (U22) and the SIO (U21). U10f's input
may be at 2.4576 MHz or 4.9152 Mhz. The MFJ-1278B operates at the faster clock of
4.9152 MHz. Capacitors C59 and C60 are used to slow the edges of the outputs of U4a, and
capacitor C61 is used to slow the edges from U10f, helping to reduce RFI.
Counter U1 is a multiple-stage divide-by-two circuit that divides the signal at its input many
times. This allows the switches within U30 and U31 to select the desired signaling (baud)
rate to be used for your computer or terminal as well as the radio channel baud rate.
The output from counter U1 at pin 12 provides a real-time clock interval signal for the SIO.
During normal operation, the SIO will be programmed to interrupt the CPU on every
transition of this 600 Hz signal. This interrupt occurs 1200 times a second, and is used for
protocol and calibration timing functions.