Epson Multi-mode Data Controller MFJ-1278B - Manual (Page 326)

MFJ-1278B MULTI-MODE PACKET RADIO PROTOCOL
Level two accomplishes this task by partitioning data to be transferred by level one into
individual frames, each with its own error detection field and frame identification fields. The
MFJ-1278B supports two versions of a level-two layer, AX.25 version 1.0 and AX.25
version 2.0. Each of these protocols is based on the High-Level Data Link Control, HDLC,
protocol defined by the ISO.
HDLC FRAMES
Exact knowledge of the format of HDLC frames is unnecessary by the advent of LSI and
VLSI communication chips that interface directly with level one hardware. The level two
software need only supply data to fill in various fields and the chip takes care of the rest. For
completeness however, an HDLC frame looks like this:
| FLAG | ADDRESS | CONTROL | PID & DATA | FCS | FLAG |
FLAG
HDLC uses a unique bit sequence (01111110) to detect frame boundaries. A technique
called "bit stuffing" is used to keep all other parts of the frame from looking like a flag.
ADDRESS
The ADDRESS field holds the specified destination address. The AX.25 protocol uses
a minimum of 14 bytes and up to a maximum of 70 bytes that contains the actual
callsign of the source, destination and optionally up to eight digipeaters.
CONTROL
The CONTROL field holds a byte that identifies the frame type. In the AX.25
protocol, the control field may include frame numbers in one or two 3-bit fields.
PID
The PID field holds the Protocol IDentification byte. The PID appears as the first byte
of the HDLC DATA field in AX.25 Level Two information frames. The PID identifies
which Level 3 protocol is implemented, if any. In the case where no Level 3 protocol is
implemented, PID = $F0.
DATA
The DATA field contains the actual information to be transferred. The DATA field
need not be present. Most frames used only for link control do not have data fields.
FCS