1 port data register (pdr), Port data register (pdr) – FUJITSU F2MCTM-16LX User Manual
Page 186
170
CHAPTER 10 I/O PORTS
10.2.1
Port Data Register (PDR)
Note that R/W for I/O ports differ from R/W for memory in the following points:
• Input mode
Read: The level at the corresponding pin is read.
Write: Data is written to an output latch.
• Output mode
Read: The port data register latch value is read.
Write: Data is written to an output latch and outputted to the corresponding pin.
Figure 10.2-2 shows the port data registers (PDR).
■
Port Data Register (PDR)
Figure 10.2-2 Port Data Registers (PDR)
P27
P26
P25
P24
P23
P22
P21
P20
P44
P43
P42
P41
P40
P54
P53
P52
P51
P50
P67
P66
P65
P64
P63
P62
P61
P60
P87
P86
P85
P84
P83
P82
P80
P57
P56
P55
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bit No.
Reset value
Access
Undefined
R/W
Undefined
R/W
Undefined
R/W
Undefined
R/W
Undefined
R/W
Bit No.
Bit No.
Bit No.
Bit No.
PDR2
Address: 000002
H
PDR4
Address: 000004
H
PDR5
Address: 000005
H
PDR6
Address: 000006
H
PDR8
Address: 000008
H