FUJITSU F2MCTM-16LX - Manual (Page 492)

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CHAPTER 21 CAN CONTROLLER
21.4.20 Reception Interrupt Enable Register (RIER)
Reception interrupt enable register (RIER) enables or disables the reception interrupt by
the message buffer (x).
The reception interrupt is generated at reception completion (when RCx of the reception
completion register (RCR) is 1).
■ Register Configuration
Figure 21.4-20 Configuration of the Reception Interrupt Enable Register (RIER)
■ Register Function
0: Reception interrupt disabled.
1: Reception interrupt enabled.
Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 RIER1(Upper)
CAN1: 00008F H RIE15 RIE14 RIE13 RIE12 RIE11 RIE10 RIE9 RIE8 Reset value
0 0 0 0 0 0 0 0
B
R/W R/W R/W R/W R/W R/W R/W R/W
Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 RIER1(Lower)
CAN1: 00008E H RIE7 RIE6 RIE5 RIE4 RIE3 RIE2 RIE1 RIE0 Reset value
0 0 0 0 0 0 0 0
B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Read/Write