FUJITSU F2MCTM-16LX User Manual
Page 307
291
CHAPTER 16 8-/16-BIT PPG TIMER
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List of Registers and Reset Values of 8-/16-bit PPG Timer
Figure 16.3-1 List of Registers and Reset Values of 8-/16-bit PPG Timer
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Generation of Interrupt Request from 8-/16-bit PPG Timer
In the 8-/16-bit PPG timer, the underflow generation flag bits in the PPG operation mode control registers
(PPGCn:PUFn, PPGCm:PUFm) are set to "1" when an underflow occurs. If the underflow interrupts of
channels causing an underflow are enabled (PPGCn: PIE0=1, PPGCm: PIE1=1), an underflow interrupt
request is generated to the interrupt controller.
15
14
bit
13
12
11
10
9
8
7
6
bit
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
15
14
bit
13
12
11
10
9
8
bit
0
1
0
0
0
0
0
15
14
bit
13
12
11
10
9
8
0
0
0
0
0
0
bit
7
6
5
4
3
2
1
0
0
1
0
0
0
bit
0
PPGm operation mode control register: H
(PPGCm)
PPGn operation mode control register: L
(PPGCn)
PPGn/m count clock select register
(PPGnm)
PPGn reload register: H(PRLHn)
PPGn reload register: L(PRLLn)
PPGm reload register: H(PRLHm)
PPGm reload register: L(PRLLm)
✕
: Undefined
n = C, E
m = D, F