FUJITSU F2MCTM-16LX - Manual (Page 79)

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CHAPTER 3 INTERRUPTS
[bit 15 to bit 12, bit 7 to bit 4] ICS 3 to ICS 0 (extended intelligent I/O service channel select bits)
ICS3 to ICS0 are write-only bits. These bits specify the EI
2
OS channel. The values set in these bits
determined the extended intelligent I/O service descriptor addresses in memory, which is explained
later. The ICS bits are initialized to "0000
B
" by a reset.
Table 3.3-2 describes the correspondence between the ICS bits, channel numbers, and descriptor
addresses.
Table 3.3-2 ICS Bits, Channel Numbers, and Descriptor Address
ICS3 ICS2 ICS1 ICS0 Selected channel Descriptor address
0 0 0 0 0 000100
H
0 0 0 1 1 000108
H
0 0 1 0 2 000110
H
0 0 1 1 3 000118
H
0 1 0 0 4 000120
H
0 1 0 1 5 000128
H
0 1 1 0 6 000130
H
0 1 1 1 7 000138
H
1 0 0 0 8 000140
H
1 0 0 1 9 000148
H
1 0 1 0 10 000150
H
1 0 1 1 11 000158
H
1 1 0 0 12 000160
H
1 1 0 1 13 000168
H
1 1 1 0 14 000170
H
1 1 1 1 15 000178
H