FUJITSU F2MCTM-16LX - Manual (Page 483)

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21.4.11 Transmission Request Register (TREQR)
Transmission request register (TREQR) stores transmission requests to the message
buffers (x) or displays their state.
■ Register Configuration
Figure 21.4-11 Configuration of the Transmission Request Register (TREQR)
■ Register Function
When 1 is written to TREQx, transmission to the message buffer (x) starts.
If RFWTx of the remote frame receiving wait register (RFWTR)
*1
is 0, transmission starts immediately.
However, if RFWTx = 1, transmission starts after waiting until a remote frame is received (RRTRx of the
remote request receiving register (RRTRR)
*1
becomes 1). Transmission starts
*2
immediately even when
RFWTx = 1, if RRTRx is already 1 when 1 is written to TREQx.
*1: For RFWTR and TRTRR, see "21.4.12 Transmission RTR Register (TRTRR)" and "21.4.13 Remote
Frame Receiving Wait Register (RFWTR)".
*2: For cancellation of transmission, see "21.4.14 Transmission Cancel Register (TCANR)" and "21.4.15
Transmission Complete Register (TCR)".
Writing 0 to TREQx is ignored.
0 is read when a Read Modify Write instruction is performed.
If clearing (to 0) at completion of the transmit operation and setting by writing 1 are concurrent, clearing is
preferred.
If 1 is written to more than 1 bit, transmission is performed, starting with the lower-numbered message
buffer (x).
TREQx is 1 while transmission is pending, and becomes 0 when transmission is completed or canceled.
Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 TREQR1(Upper)
CAN1: 000083 H TREQ15 TREQ14 TREQ13 TREQ12 TREQ11 TREQ10 TREQ9 TREQ8 Reset value
0 0 0 0 0 0 0 0
B
R/W R/W R/W R/W R/W R/W R/W R/W
Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TREQR1(Lower)
CAN1: 000082 H TREQ7 TREQ6 TREQ5 TREQ4 TREQ3 TREQ2 TREQ1 TREQ0 Reset value
0 0 0 0 0 0 0 0
B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Read/Write