FUJITSU F2MCTM-16LX - Manual (Page 248)

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CHAPTER 13 16-Bit I/O TIMER
Figure 13.6-2 Timing of Fetching Data for Input Capture
Figure 13.6-3 Operation of Input Capture (Rising edge/falling edge)
Figure 13.6-4 Operation of Input Capture (both edges)
N
N+1
N+1
φ
: Machine clock
Data fetch
φ
Input capture input
Capture signal
Capture register
Counter value
Valid edge
F F F F H
B F F F H
7 F F F
H
3 F F F
H
0 0 0 0 H
7FFF
H
3FFF H
Counter value
Reset
Time
INn (rising edge)
Capture n
Undefined
Undefined
INm (falling edge)
Capture m
n = 0, 2 m = n+1
F F F F H
B F F F
H
7 F F F
H
3 F F F
H
0 0 0 0 H
BFFF H 3FFF H
Counter value
Reset
Time
INn (both edge)
Capture example Undefined
n = 0 to 3