Mitac secret confidential document – MiTAC 8050QMA User Manual
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N/B Maintenance
N/B Maintenance
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Supports tight ppm accuracy clocks for Serial-ATA and SRC.
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Supports spread spectrum modulation, 0 to –0.5% down spread.
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Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning.
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Supports undriven differential CPU, SRC pair in PD# for power management.
1.2.3 The Mobile Intel 915PM Express Chipset
The Mobile Intel 915PM Express Chipset integras a memory controller hub (MCH) designed for use with the
Dothan, Yonah and Intel Celeron M Processor. It is PCI Express based Graphics.
The 915PM MCH integrates a system memory DDR/DDR2 controller with two, 64-bit wide interfaces. Only
Double Data Rate (DDR/DDR2) memory is supported; the buffers support DDR SSTL_2 and DDR2 SSTL_18
signaling interfaces. The memory controller interface is fully configurable through a set of control registers. It
integras a high performance transition interface PCI Express Interface. PCI Express operates at a data rate of 2.5
for 8050QMA project. GB/s. This allows a maximum theoretical bandwidth of 40 GB/s each direction. The 915PM
MCH integrates Direct media interface (DMI) chip-to-chip interconnect between the MCH and ICH6-M. DMI
supports DMI x2 and DMI x4 configuration.
Features:
Processor/FSB Support
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