Mitac secret confidential document – MiTAC 8050QMA User Manual
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50QMA
50QMA
N/B Maintenance
N/B Maintenance
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Intel
®
Dothan processor
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AGTL+ bus driver technology with integrated GTL termination resistors (gated AGTL+ receivers for reduced
power)
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Supports 32-bit AGTL+ host bus addressing
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Supports system bus at 533MT/s (533 MHz) and 400MT/s (400 MHz)
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2X Address, 4X data
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Host bus dynamic bus inversion HDINV support
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12 deep, in-order queue
Memory System
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Directly supports to two DDR or DDR2 SDRAM channels, 64-bts wide.
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Supports SO-DIMMs of the same type (e.g.,all DDR or all DDR2), not mixed.
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Maximum of two, double-sided unbuffered SO-DIMMs (4 rows populated)
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Minimum amount of memory supported is 128 MB (16 MB x 16-b x 4 devices x 1 rows = 128 MB) using
256-MB technology
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Maximum amount of memory supported is 2 GB using 1-GB technology.
MiTac Secret
Confidential Document