MiTAC 8050QMA - Manual (Page 83)

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5.1 Intel 915PM North Bridge(5)
DDR / DDR2 Common Signals
Signal Name Type Description
SM_CK[1:0],
SM_CK[4:3] O
SSTL1.8/2
SDRAM Differential Clock:
The crossing of the positive edge of SM_CKx and the negative edge
of its complement SM_CKx# are used to sample the command and
control signals on the SDRAM.
SM_CK[0:1] and its complement SM_CK[1:0]# signal make a
differential clock pair output.
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
SM_CK[4:3] and its complement SM_CK[4:3]# signal make a
differential clock pair output.
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B
NOTE: SM_CK2 and SM_CK5 are reserved and not supported.
SM_CK[1:0]#,
SM_CK[4:3]# O
SSTL1.8/2
SDRAM Inverted Differential Clock:
These are the complementary Differential DDR2 Clock signals.
NOTE: SM_CK2# and SM_CK5# are reserved and not supported.
SM_CS[3:0]# O
SSTL1.8/2
Chip Select: (1 per Rank):
These signals select particular SDRAM components during the active
state. There is one Chip Select for each SDRAM rank
SM_CS[1:0]# :
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
SM_CS[3:2]# :
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B
SM_CKE[3:0] O
SSTL1.8/2
Clock Enable: (1 per Rank):
SM_CKE[3:0] is used:
.To initialize the SDRAMs during power-up
.To power-down SDRAM ranks
. To place all SDRAM ranks into and out of self-refresh during STR.
SM_CKE[1:0]:
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
SM_CKE[3:2]:
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B
DDR / DDR2 Common Signals (Continued)
Signal Name Type Description
SM_ODT[3:0] O
SSTL1.8/2
On Die Termination: Active Termination Control. (DDR2 only)
SM_ODT[1:0]:
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
Signal Description
The crossing of the positive edge of SM_CKx and the negative edge
of its
complement SM_CKx# are used to sample the command and control
SM_CK[0:1] and its complement SM_CK[1:0]# signal make a
differential
SM_CK[4:3] and its complement SM_CK[4:3]# signal make a
differential
NOTE: SM_CK2 and SM_CK5 are reserved and not supported.
These are the complementary Differential DDR2 Clock signals.
NOTE: SM_CK2# and SM_CK5# are reserved and not supported.
These signals select particular SDRAM components during the active
To place all SDRAM ranks into and out of self-refresh during STR.
On Die Termination: Active Termination Control. (DDR2 only)
SM_ODT[3:2]:
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B
DDR: Leave as no connects. Not used for DDR devices.
DDR2: On-die termination for DDR2 devices.
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