MiTAC 8050QMA - Manual (Page 29)

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80 80 50QMA 50QMA N/B Maintenance N/B Maintenance
2. Supports PCI clock 16.75MHz-40MHz
3. Supports PCI target fast back-to-back transaction
4. Provides PCI bus master data transfers and PCI memory space or I/O space mapped data transfers of
RTL8100C(L)'s operational registers
5. Supports PCI VPD (Vital Product Data)
6. Supports ACPI, PCI power management
• Supports 25MHz crystal or 25MHz OSC as the internal clock source. The frequency deviation of either crystal
or OSC must be within 50 PPM.
• Compliant to PC99/PC2001 standard
•
Supports Wake-On-LAN function and remote wake-up (Magic Packet*, LinkChg and Microsoft® wake-up
frame)
• Supports 4 Wake-On-LAN (WOL) signals (active high, active low, positive pulse and negative pulse)
• Supports auxiliary power-on internal reset, to be ready for remote wake-up when main power still remains off
• Supports auxiliary power auto-detect, and sets the related capability of power management registers in PCI
configuration space
• Includes a programmable, PCI burst size and early Tx/Rx threshold
• Supports a 32-bit general-purpose timer with the external PCI clock as clock source, to generate timer-interrupt
• Contains two large (2Kbyte) independent receive and transmit FIFOs
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