Mitac secret confidential document, 5 appendix 1: intel ich6-m gpio definitions (1) – MiTAC 8050QMA User Manual
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1.5 Appendix 1: Intel ICH6-M GPIO Definitions (1)
Pin name
Current Define
Power plane
GPIO0 PCI_REQ6#
I
MAIN
GPIO1 MINIPCI_ACT#
I
MAIN
GPIO2 PCI_INTE#
I
MAIN
GPIO3 PCI_INTF#
I
MAIN
GPIO4 PCI_INTG#
I
MAIN
GPIO5 PCI_INTH#
I
MAIN
GPIO6 PM_BMBUSY#
I
MAIN
GPIO9 X
I
RESUME
GPIO10 X
I
RESUME
GPIO11 SMBALERT#
I
RESUME
GPIO12 KBD_US/JP#
I
MAIN
GPIO13 WAKE_UP#
I
RESUME
GPIO14 X
I
RESUME
GPIO15 X
I
RESUME
GPIO16 SB_BY_ON#
O
MAIN
GPIO17 SCI#
I
MAIN
GPIO18 STOP_PCI#
O
MAIN
GPIO20 STOP_CPU#
O
MAIN
GPIO23 WIRELESS_PD#
O
MAIN
GPIO24 SPK_OFF
I/O
RESUME
GPIO25
I/O RESUME
GPIO26 PANEL_ID0
I
MAIN
GPIO27 X
I/O RESUME
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