NEC switch - Manual (Page 10)

User’s Manual U12978EJ3V0UD
10
TABLE OF CONTENTS
CHAPTER 1 GENERAL.......................................................................................................................... 21
1.1 Features ...................................................................................................................................... 21
1.2 Applications................................................................................................................................ 21
1.3 Ordering Information ................................................................................................................. 21
1.4 Pin Configuration (Top View).................................................................................................... 22
1.5 78K/0S Series Lineup................................................................................................................. 23
1.6 Block Diagram ............................................................................................................................ 26
1.7 Functions .................................................................................................................................... 27
CHAPTER 2 PIN FUNCTIONS .............................................................................................................. 28
2.1 List of Pin Functions.................................................................................................................. 28
2.2 Pin Functions ............................................................................................................................. 30
2.2.1 P00 to P07 (Port 0) ....................................................................................................................... 30
2.2.2 P10 to P17 (Port 1) ....................................................................................................................... 30
2.2.3 P20 to P26 (Port 2) ....................................................................................................................... 30
2.2.4 P40 to P47 (Port 4) ....................................................................................................................... 31
2.2.5 RESET.......................................................................................................................................... 31
2.2.6 X1, X2 ........................................................................................................................................... 31
2.2.7 REGC ........................................................................................................................................... 31
2.2.8 USBDM......................................................................................................................................... 31
2.2.9 USBDP ......................................................................................................................................... 31
2.2.10 V DD0 , V DD1 .................................................................................................................................... 31
2.2.11 V
SS0
, V
SS1
..................................................................................................................................... 31
2.2.12 V PP (
µPD78F9801 only) ................................................................................................................ 32
2.2.13 IC (mask ROM version only)......................................................................................................... 32
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ......................................... 33
CHAPTER 3 CPU ARCHITECTURE ..................................................................................................... 35
3.1 Memory Space ............................................................................................................................ 35
3.1.1 Internal program memory space ................................................................................................... 37
3.1.2 Internal data memory (internal high-speed RAM) space .............................................................. 37
3.1.3 Special function register (SFR) area............................................................................................. 37
3.1.4 Data memory addressing.............................................................................................................. 38
3.2 Processor Registers .................................................................................................................. 40
3.2.1 Control registers ........................................................................................................................... 40
3.2.2 General-purpose registers ............................................................................................................ 43
3.2.3 Special function registers (SFRs) ................................................................................................. 44
3.3 Instruction Address Addressing .............................................................................................. 48
3.3.1 Relative addressing ...................................................................................................................... 48
3.3.2 Immediate addressing .................................................................................................................. 49
3.3.3 Table indirect addressing ............................................................................................................. 50