NEC switch - Manual (Page 101)

CHAPTER 8 USB FUNCTION
User’s Manual U12978EJ3V0UD
101
(1) Receive bank switching ID detection buffer (internal buffer)
This is an internal 2-bit buffer placed before a receive buffer. It detects the lower 2 bits below the packet ID
during packet reception and determines the store bank of a packet.
The following controls are performed depending on the stored 2-bit data. For details, see Section 8.5.3 Receive
bank switching ID detection buffer operation.
<1> If the first 2 bits of the stored bits (lower 2 bits in ID area) are 01B, TOSTAT (bit 0 of the packet receive
status register (RXSTAT)) indicating token packet reception is set and a signal specifying packet store
at the receive token address is output to the transmit/receive pointer.
<2> If the first 2 bits of the stored bits are 11B, DASTAT (bit 1 of RXSTAT) indicating data packet reception
is set and a signal specifying packet store at the receive data address is sent to the transmit/receive
pointer.
<3> If the first 2 bits of the stored bits are 10B, HSSTAT (bit 2 of RXSTAT) indicating handshake packet
reception is set and a signal specifying packet store at the receive data address is output to the
transmit/receive pointer.
(2) Transmit/receive pointer (USBPOB and USBPOW)
The USBPOB is a pointer on the bit side in the transmit/receive buffer and the USBPOW is a pointer on the
word side of the transmit/receive buffer. USBPOB and USBPOW output a control signal to the CRC circuit, etc.
They are reset and started by the packet ID detection signal from the receive bank switching ID detection buffer.
USBPOB is incremented by the USB clock. USBPOW is incremented by USBPOB overflow.
USBPOW is read with an 8-bit memory manipulation instruction. As USBPOB is an internal pointer, control with
software is not possible.
RESET input sets these pointers to 00H.
The value of USBPOW is changed as follows depending on the receive/transmit byte length match signal or
transmit reservation. Moreover, control signals are also output. For details, see Section 8.8.1 Operation of
transmit/receive pointer.
• If the token packet receive signal is detected by the receive bank switching ID detection buffer, the pointers
are set to 00H.
• If the data/handshake packet receive signal is detected by the receive bank switching ID detection buffer, the
pointers are set to 10H.
• If USBPOW is set to 01H, a signal specifying CRC5 (CRC5 bit mode) execution start is output.
• If USBPOW is set to 11H, 21H, or 31H, a signal specifying CRC16 (CRC16 bit mode) execution start is
output.
• If USBPOB is set to 02H after USBPOW is set to 02H, a signal specifying CRC5 comparison start is output
and USBPOW is set to 70H.
• If the value of USBPOW matches that of the data/handshake packet receive byte number counter
(DRXCON), a signal specifying CRC16 comparison start is output when USBPOB overflows, and USBPOW
is set to 70H.
• If a signal specifying transmit start is received from the transmit controller, USBPOW is set to 7FH. After that,
USBPOW is set to 20H, 30H, 40H, 50H, or 60H depending on the error between the present transmit
reservation and previous receive data, when USBPOB overflows.
• If the value of USBPOW matches that of data packet transmit byte number counter 0 (DTXCO0) or data
packet transmit byte number counter 1 (DTXCO1), USBPOW is set to 70H when USBPOB overflows (CRC
redundant bits are appended).
• USBPOW is set to 71H, then a signal specifying EOP transmission is output when USBPOB overflows.
• When USBPOW is set to 40H, 50H, or 60H, a signal specifying EOP transmission is output if USBPOB
overflows.