NEC switch - Manual (Page 95)

CHAPTER 7 WATCHDOG TIMER
User’s Manual U12978EJ3V0UD
95
7.4 Watchdog Timer Operation
7.4.1 Operation as watchdog timer
The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode
register (WDTM) is set to 1.
The count clock (inadvertent loop detection time interval) of the watchdog timer can be selected by bits 0 to 2
(TCL20 to TCL22) of timer clock select register 2 (TCL2). By setting bit 7 (RUN) of WDTM to 1, the watchdog timer
is started. Set RUN to 1 within the set inadvertent loop detection time interval after the watchdog timer has been
started. By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1, and the
inadvertent loop detection time is exceeded, the system is reset or a non-maskable interrupt is generated by the
value of bit 3 (WDTM3) of WDTM.
The watchdog timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to
1 before entering the STOP mode to clear the watchdog timer, and then execute the STOP instruction.
Caution The actual inadvertent loop detection time may be up to 0.8% shorter than the set time.
Table 7-4. Inadvertent Loop Detection Time of Watchdog Timer
TCL22 TCL21 TCL20 Inadvertent Loop Detection Time Operation at f X = 6.0 MHz
0 0 0 2 11 × 1/f
X
341 µs
0 1 0 2 13 × 1/f
X
1.37 ms
1 0 0 2 15 × 1/f
X
5.46 ms
1 1 0 2 17 × 1/f
X
21.8 ms
f
X
: System clock oscillation frequency