Section 5.22 – Texas Instruments TMS320DM36X User Manual
Page 104
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Ethernet Media Access Controller (EMAC) Registers
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5.22 Receive Unicast Enable Set Register (RXUNICASTSET)
The receive unicast enable set register (RXUNICASTSET) is shown in
and described in
.
Figure 61. Receive Unicast Enable Set Register (RXUNICASTSET)
31
16
Reserved
R-0
15
8
Reserved
R-0
7
6
5
4
3
2
1
0
RXCH7EN
RXCH6EN
RXCH5EN
RXCH4EN
RXCH3EN
RXCH2EN
RXCH1EN
RXCH0EN
R/W1S-0
R/W1S-0
R/W1S-0
R/W1S-0
R/W1S-0
R/W1S-0
R/W1S-0
R/W1S-0
LEGEND: R = Read only; R/W = Read/Write; W1S = Write 1 to set, write of 0 has no effect; -n = value after reset
Table 59. Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7
RXCH7EN
0-1
Receive channel 7 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect.
May be read.
6
RXCH6EN
0-1
Receive channel 6 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect.
May be read.
5
RXCH5EN
0-1
Receive channel 5 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect.
May be read.
4
RXCH4EN
0-1
Receive channel 4 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect.
May be read.
3
RXCH3EN
0-1
Receive channel 3 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect.
May be read.
2
RXCH2EN
0-1
Receive channel 2 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect.
May be read.
1
RXCH1EN
0-1
Receive channel 1 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect.
May be read.
0
RXCH0EN
0-1
Receive channel 0 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect.
May be read.
104
Ethernet Media Access Controller (EMAC)/Management Data Input/Output
SPRUFI5B – March 2009 – Revised December 2010
(MDIO)
© 2009–2010, Texas Instruments Incorporated