Texas Instruments TMS320DM36X - Manual (Page 67)

www.ti.com EMAC Control Module Registers
3.11 EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT)
The transmit interrupt status register (CMTXINTSTAT) is shown in Figure 22 and described in Table 18 .
Figure 22. EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT)
31 16
Reserved
R-0
15 8 7 0
Reserved TXPULSEINTTSTAT
R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 18. EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT)
Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7-0 TXPULSEINTTSTAT[n] Transmit interrupt status. Each bit shows the status of the corresponding channel n transmit
interrupt.
Bit n = 0, channel n transmit interrupt is not pending.
Bit n = 1, channel n transmit interrupt is pending.
67 SPRUFI5B – March 2009 – Revised December 2010 Ethernet Media Access Controller (EMAC)/Management Data Input/Output
(MDIO)
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