Section 5.8 – Texas Instruments TMS320DM36X User Manual
Page 91
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Ethernet Media Access Controller (EMAC) Registers
5.8
Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)
The transmit interrupt status (masked) register (TXINTSTATMASKED) is shown in
and
described in
.
Figure 47. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)
31
16
Reserved
R-0
15
8
Reserved
R-0
7
6
5
4
3
2
1
0
TX7PEND
TX6PEND
TX5PEND
TX4PEND
TX3PEND
TX2PEND
TX1PEND
TX0PEND
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 45. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7
TX7PEND
0-1
TX7PEND masked interrupt read
6
TX6PEND
0-1
TX6PEND masked interrupt read
5
TX5PEND
0-1
TX5PEND masked interrupt read
4
TX4PEND
0-1
TX4PEND masked interrupt read
3
TX3PEND
0-1
TX3PEND masked interrupt read
2
TX2PEND
0-1
TX2PEND masked interrupt read
1
TX1PEND
0-1
TX1PEND masked interrupt read
0
TX0PEND
0-1
TX0PEND masked interrupt read
91
SPRUFI5B – March 2009 – Revised December 2010
Ethernet Media Access Controller (EMAC)/Management Data Input/Output
(MDIO)
© 2009–2010, Texas Instruments Incorporated