Texas Instruments TMS320DM36X - Manual (Page 122)

Ethernet Media Access Controller (EMAC) Registers www.ti.com
5.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP)
The transmit channel 0-7 completion pointer register (TXnCP) is shown in Figure 87 and described in
Table 85 .
Figure 87. Transmit Channel n Completion Pointer Register (TXnCP)
31 16
TXnCP
R/W-x
15 0
TXnCP
R/W-x
LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset
Table 85. Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions
Bit Field Value Description
31-0 TXnCP 0-FFFF FFFFh Transmit channel n completion pointer register is written by the host with the buffer descriptor
address for the last buffer processed by the host during interrupt processing. The EMAC uses the
value written to determine if the interrupt should be deasserted.
5.49 Receive Channel 0-7 Completion Pointer Register (RXnCP)
The receive channel 0-7 completion pointer register (RXnCP) is shown in Figure 88 and described in
Table 86 .
Figure 88. Receive Channel n Completion Pointer Register (RXnCP)
31 16
RXnCP
R/W-x
15 0
RXnCP
R/W-x
LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset
Table 86. Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions
Bit Field Value Description
31-0 RXnCP 0-FFFF FFFFh Receive channel n completion pointer register is written by the host with the buffer descriptor
address for the last buffer processed by the host during interrupt processing. The EMAC uses the
value written to determine if the interrupt should be deasserted.
122 Ethernet Media Access Controller (EMAC)/Management Data Input/Output SPRUFI5B – March 2009 – Revised December 2010
(MDIO)
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