Texas Instruments TMS320DM36X - Manual (Page 16)

EMAC_TX_CLK
EMAC_TXD(3-0)
EMAC_TX_EN
EMAC_COL
EMAC_CRS
EMAC_RX_CLK
EMAC_RXD(3-0)
EMAC_RX_DV
MRXER
MDCLK
MDIO
Physical
layer
device
(PHY)
System
core Transformer
2.5 MHz,
25 MHz
RJ-45
EMAC
MDIO
_
Architecture www.ti.com
2.2 Memory Map
The EMAC peripheral includes internal memory that is used to hold information about the Ethernet
packets received and transmitted. This internal RAM is 2K × 32 bits in size. Data can be written to and
read from the EMAC internal memory by either the EMAC or the CPU. It is used to store buffer descriptors
that are 4-words (16-bytes) deep. This 8K local memory holds enough information to transfer up to 512
Ethernet packets without CPU intervention.
The packet buffer descriptors can also be placed in the internal processor memory (L2), or in EMIF
memory (DDR). There are some tradeoffs in terms of cache performance and throughput when
descriptors are placed in the system memory, versus when they are placed in the EMAC’s internal
memory. Cache performance is improved when the buffer descriptors are placed in internal memory.
However, the EMAC throughput is better when the descriptors are placed in the local EMAC RAM.
2.3 Signal Descriptions
The DM36x DMSoC supports the MII interface (for 10/100 Mbps) operation.
2.3.1 Media Independent Interface (MII) Connections
Figure 2 shows a device with integrated EMAC and MDIO interfaced via a MII connection. The EMAC
module does not include a transmit error (MTXER) pin. In the case of transmit error, CRC inversion is
used to negate the validity of the transmitted frame.
The individual EMAC and MDIO signals for the MII interface are summarized in Table 1 . For more
information, refer to either the IEEE 802.3 standard or ISO/IEC 8802-3:2000(E).
Figure 2. Ethernet Configuration MII Connections
16 Ethernet Media Access Controller (EMAC)/Management Data Input/Output SPRUFI5B – March 2009 – Revised December 2010
(MDIO)
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