Texas Instruments TMS320DM36X - Manual (Page 79)

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4.11 MDIO User Access Register 0 (USERACCESS0)
The MDIO user access register 0 (USERACCESS0) is shown in Figure 36 and described in Table 33 .
Figure 36. MDIO User Access Register 0 (USERACCESS0)
31 30 29 28 26 25 21 20 16
GO WRITE ACK Reserved REGADR PHYADR
R/W1S-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0
15 0
DATA
R/W-0
LEGEND: R = Read only; R/W = Read/Write; W1S = Write 1 to set, write of 0 has no effect; -n = value after reset
Table 33. MDIO User Access Register 0 (USERACCESS0) Field Descriptions
Bit Field Value Description
31 GO 0-1 Go bit. Writing a 1 to this bit causes the MDIO state machine to perform an MDIO access when it
is convenient for it to do so; this is not an instantaneous process. Writing a 0 to this bit has no
effect. This bit is writeable only if the MDIO state machine is enabled. This bit will self clear when
the requested access has been completed. Any writes to the USERACCESS0 register are blocked
when the GO bit is 1.
30 WRITE Write enable bit. Setting this bit to 1 causes the MDIO transaction to be a register write; otherwise,
it is a register read.
0 The user command is a read operation.
1 The user command is a write operation.
29 ACK 0-1 Acknowledge bit. This bit is set if the PHY acknowledged the read transaction.
28-26 Reserved 0 Reserved
25-21 REGADR 0-1Fh Register address bits. This field specifies the PHY register to be accessed for this transaction
20-16 PHYADR 0-1Fh PHY address bits. This field specifies the PHY to be accessed for this transaction.
15-0 DATA 0-FFFFh User data bits. These bits specify the data value read from or to be written to the specified PHY
register.
79 SPRUFI5B – March 2009 – Revised December 2010 Ethernet Media Access Controller (EMAC)/Management Data Input/Output
(MDIO)
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