Texas Instruments TMS320DM36X - Manual (Page 63)

www.ti.com EMAC Control Module Registers
3.5 EMAC Control Module Receive Threshold Interrupt Enable Register
(CMRXTHRESHINTEN)
The receive threshold interrupt enable register (CMRXTHRESHINTEN) is shown in Figure 16 and
described in Table 12 .
Figure 16. EMAC Control Module Receive Threshold Interrupt Enable Register
(CMRXTHRESHINTEN)
31 16
Reserved
R-0
15 8 7 0
Reserved RXTHRESHEN
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. EMAC Control Module Receive Threshold Interrupt Enable Register
(CMRXTHRESHINTEN) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7-0 RXTHRESHEN[n] Receive threshold interrupt (RXTHRESHPENDn) enable. Each bit controls the corresponding
channel n receive threshold interrupt.
Bit n = 0, channel n receive threshold interrupt (RXTHRESHPENDn) is disabled.
Bit n = 1, channel n receive threshold interrupt (RXTHRESHPENDn) is enabled.
3.6 EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN)
The receive interrupt enable register (CMRXINTEN) is shown in Figure 17 and described in Table 13 .
Figure 17. EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN)
31 16
Reserved
R-0
15 8 7 0
Reserved RXPULSEEN
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN)
Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7-0 RXPULSEEN[n] Receive interrupt (RXPENDn) enable. Each bit controls the corresponding channel n receive
interrupt.
Bit n = 0, channel n receive interrupt (RXPENDn) is disabled.
Bit n = 1, channel n receive interrupt (RXPENDn) is enabled.
63 SPRUFI5B – March 2009 – Revised December 2010 Ethernet Media Access Controller (EMAC)/Management Data Input/Output
(MDIO)
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