Texas Instruments TMS320DM36X - Manual (Page 99)

www.ti.com Ethernet Media Access Controller (EMAC) Registers
5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)
The MAC interrupt status (unmasked) register (MACINTSTATRAW) is shown in Figure 56 and
described in Table 54 .
Figure 56. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)
31 16
Reserved
R-0
15 2 1 0
Reserved HOSTPEND STATPEND
R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 54. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1 HOSTPEND 0-1 Host pending interrupt (HOSTPEND); raw interrupt read (before mask)
0 STATPEND 0-1 Statistics pending interrupt (STATPEND); raw interrupt read (before mask)
5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)
The MAC interrupt status (masked) register (MACINTSTATMASKED) is shown in Figure 57 and
described in Table 55 .
Figure 57. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)
31 16
Reserved
R-0
15 2 1 0
Reserved HOSTPEND STATPEND
R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 55. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1 HOSTPEND 0-1 Host pending interrupt (HOSTPEND); masked interrupt read
0 STATPEND 0-1 Statistics pending interrupt (STATPEND); masked interrupt read
99 SPRUFI5B – March 2009 – Revised December 2010 Ethernet Media Access Controller (EMAC)/Management Data Input/Output
(MDIO)
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