Texas Instruments TMS320DM36X - Manual (Page 55)

EMAC core
MDIO core
RXTHRESHOLDPEND(0..7)
Receive threshold interrupt
RXPEND(0..7)
Receive interrupt
TXPEND(0..7)
Transmit interrupt
STATPEND
HOSTPEND
MDIO_USER
Miscellaneous interrupt
MDIO_LINKINT
Interrupt control and pacing logic
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2.17 Interrupt Support
2.17.1 EMAC Module Interrupt Events and Requests
The EMAC module generates the following interrupt events:
•
RXTHRESHOLDPENDn: Receive threshold interrupt for receive channels 0 through 7
• RXPENDn: Receive packet completion interrupt for receive channels 0 through 7
• TXPENDn: Transmit packet completion interrupt for transmit channels 0 through 7
• STATPEND: Statistics interrupt
• HOSTPEND: Host error interrupt
• USERINT: MDIO user Interrupt
• LINKINT: MDIO link Interrupt
As shown in Figure 11 , the EMAC and MDIO interrupts are multiplexed on four interrupts lines going to
the CPU.
Figure 11. EMAC Control Module Interrupt Logic Diagram
2.17.1.1 Receive Threshold Interrupts
Each of the eight receive channels have a corresponding receive threshold interrupt
(RX_THRESH_PEND[0:7]). The receive threshold interrupts are level interrupts that remain asserted
until the triggering condition is cleared by the host. Each of the eight threshold interrupts may be
individually enabled by setting the corresponding bit in the receive interrupt mask set register
(RXINTMASKSET) to 1. Each of the eight channel interrupts may be individually disabled by clearing
the corresponding bit in the receive interrupt mask clear register (RXINTMASKCLEAR) to 0. The raw
and masked receive interrupt status may be read from the receive interrupt status (unmasked) register
(RXINTSTATRAW) and the receive interrupt status (masked) register (RXINTSTATMASKED),
respectively. An RX_THRES_PEND[7:0] interrupt bit is asserted when enabled and when the channel’s
associated receive channel n free buffer count register (RXnFREEBUFFER) is less than or equal to the
channel’s associated receive channel n flow control threshold register (RXnFLOWTHRESH). The
receive threshold interrupts use the same free buffer count and threshold logic as does flow control, but
the interrupts are independently enabled from flow control. The threshold interrupts are intended to give
the host an indication that resources are running low for a particular channel(s).
2.17.1.2 Transmit Packet Completion Interrupts
The transmit DMA engine has eight channels, with each channel having a corresponding interrupt
(TXPENDn). The transmit interrupts are level interrupts that remain asserted until cleared by the CPU.
55 SPRUFI5B – March 2009 – Revised December 2010 Ethernet Media Access Controller (EMAC)/Management Data Input/Output
(MDIO)
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