Texas Instruments TMS320DM36X - Manual (Page 62)

EMAC Control Module Registers www.ti.com
3.4 EMAC Control Module Interrupt Control Register (CMINTCTRL)
The interrupt control register (CMINTCTRL) is shown in Figure 15 and described in Table 11 .
Figure 15. EMAC Control Module Interrupt Control Register (CMINTCTRL)
31 30 18 17 16
Reserved Reserved INTPACEEN
R/W-0 R-0 R/W-0
15 12 11 0
Reserved INTPRESCALE
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. EMAC Control Module Interrupt Control Register (CMINTCTRL)
Field Descriptions
Bit Field Value Description
31 Reserved 0 Reserved
30-18 Reserved 0 Reserved
17-16 INTPACEEN 0-3h Interrupt pacing enable.
Bit 16 = 1; enables Rx_Pulse Pacing; = 0, disables pacing
Bit 17 = 1; enables Tx_Pulse Pacing; = 0, disables pacing
15-12 Reserved 0 Reserved
11-0 INTPRESCALE 0-7FFh Interrupt counter prescaler. The number of peripheral clock periods in 4 m s.
62 Ethernet Media Access Controller (EMAC)/Management Data Input/Output SPRUFI5B – March 2009 – Revised December 2010
(MDIO)
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