Document Outline

• CS485xx Hardware User’s Manual
  • Contents
  • Figures
  • Tables
  • Chapter 1: Introduction
    • 1.1 Overview
      • 1.1.1 Chip Features
    • 1.2 Code Overlays
    • 1.3 Functional Overview of the CS485xx Chip
      • 1.3.1 DSP Core
      • 1.3.2 Debug Controller (DBC)
      • 1.3.3 Digital Audio Output (DAO) Controller
      • 1.3.4 Digital Audio Input (DAI) Controller
      • 1.3.5 Direct Stream Digital (DSD) Controller
      • 1.3.6 General Purpose I/O
      • 1.3.7 Serial Control Ports (SPI™ or I2C™ Standards)
      • 1.3.8 Serial Flash Controller
      • 1.3.9 DMA Controller
      • 1.3.10 Internal Timers
      • 1.3.11 Watchdog Timer
      • 1.3.12 Clock Manager and PLL
      • 1.3.13 Programmable Interrupt Controller
  • Chapter2: Operational Modes
    • 2.1 Introduction
    • 2.2 Operational Mode Selection
    • 2.3 Slave Boot Procedures
      • 2.3.1 Slave Boot
      • 2.3.2 Performing a Slave Boot
        • 2.3.2.1 Slave Boot Procedure
      • 2.3.3 Boot Messages
        • 2.3.3.1 Slave Boot
        • 2.3.3.2 Soft Reset
        • 2.3.3.3 Messages Read from CS485xx
    • 2.4 Master Boot Procedure
    • 2.5 Softboot
      • 2.5.1 Softboot Messaging
      • 2.5.2 Softboot Procedure
        • 2.5.2.1 Softboot Steps
        • 2.5.2.2 Softboot Example
          • 2.5.2.2.1 Softboot Example Procedure
    • 2.6 Low Power Mode
      • 2.6.1 Low Power Mode Messaging
      • 2.6.2 Getting into Low Power Mode
      • 2.6.3 Getting Out of Low Power Mode
  • Chapter 3: Serial Control Port
    • 3.1 Introduction
    • 3.2 Serial Control Port Configuration
      • 3.2.1 I2C Port
      • 3.2.2 I2C System Bus Description
        • 3.2.2.1 I2C Bus Dynamics
        • 3.2.2.2 I2C Messaging
          • 3.2.2.2.1 SCP_BSY Behavior
        • 3.2.2.3 Performing a Serial I2C Write
          • 3.2.2.3.1 I2C Write Protocol Procedure
        • 3.2.2.4 Performing a Serial I2C Read
          • 3.2.2.4.1 I2C Read Protocol Procedure
          • 3.2.2.4.2 SCP_IRQ Behavior
    • 3.3 SPI Port
      • 3.3.1 SPI System Bus Description
        • 3.3.1.1 SPI Bus Dynamics
          • 3.3.1.1.1 SCP_BSY Behavior
        • 3.3.1.2 SPI Messaging
        • 3.3.1.3 Performing a Serial SPI Write
          • 3.3.1.3.1 SPI Write Protocol Procedure
        • 3.3.1.4 Performing a Serial SPI Read
          • 3.3.1.4.1 SPI Read Protocol Procedure
          • 3.3.1.4.2 SCP_IRQ Behavior
  • Chapter 4: Digital Audio Input Interface
    • 4.1 Introduction
    • 4.2 Digital Audio Input Port Description
      • 4.2.1 DAI Pin Description
      • 4.2.2 Supported DAI Functional Blocks
        • 4.2.2.1 Dual Clock Domain - 10 Channel Input
        • 4.2.2.2 Single Clock Domain - 12 Channel Input
      • 4.2.3 Digital Audio Formats
        • 4.2.3.1 I2S Format
        • 4.2.3.2 Left-Justified Format
    • 4.3 DAI Hardware Configuration
      • 4.3.1 DAI Hardware Naming Convention
  • Chapter 5: Direct Stream Data (DSD) Input Interface
    • 5.1 Digital Audio Input Port Description
      • 5.1.1 DSD Pin Description
      • 5.1.2 Supported DSD Functional Blocks
  • Chapter 6: Digital Audio Output Interface
    • 6.1 Introduction
    • 6.2 Digital Audio Output Port Description
      • 6.2.1 DAO Pin Description
      • 6.2.2 Supported DAO Functional Blocks
      • 6.2.3 DAO Interface Formats
        • 6.2.3.1 I2S Format
        • 6.2.3.2 Left-Justified Format
        • 6.2.3.3 One-line Data Mode Format (Multichannel)
      • 6.2.4 DAO Hardware Configuration
      • 6.2.5 S/PDIF Transmitter
  • Chapter 7: Crystal Oscillator and System Clocking
    • 7.1 System Clocking Controls
    • 7.2 Configuring the Crystal Oscillator
      • 7.2.1 Crystal Oscillator Hardware Configuration Messages
  • Chapter 8: General Purpose Input/Output Pins
    • 8.1 Introduction
    • 8.2 GPIO Description
    • 8.3 Watchdog Timer Description
  • Chapter 9: System Integration
    • 9.1 Typical Connection Diagrams
    • 9.2 Pin Description
      • 9.2.1 Power and Ground
        • 9.2.1.1 Power
        • 9.2.1.2 Ground
        • 9.2.1.3 Decoupling
      • 9.2.2 PLL Filter
        • 9.2.2.1 Analog Power Conditioning
      • 9.2.3 PLL
    • 9.3 Clocking
    • 9.4 Control
      • 9.4.1 Operational Mode
    • 9.5 48-Pin LQFP Pin Assigments
    • 9.6 Pin Assignments
    • Revision History