Document Outline

• CS4953xx Hardware User's Manual
  • Contents
  • Figures
  • Tables
  • Chapter 1: Introduction
    • 1.1 Overview
      • 1.1.1 Chip Features
    • 1.2 Functional Overview of the CS4953xx Chip
      • 1.2.1 DSP Core
      • 1.2.2 Security Extension module
      • 1.2.3 Debug Controller (DBC)
      • 1.2.4 Digital Audio Output (DAO1, DAO2) Controller
      • 1.2.5 Digital Audio Input (DAI1) Controller
      • 1.2.6 Compressed Data Input / Digital Audio Input (DAI2) Controller
      • 1.2.7 Direct Stream Digital® (DSD) Controller
      • 1.2.8 General Purpose I/O
      • 1.2.9 Parallel Control Port (Motorola®/Intel® Standards) (Optional Feature)
      • 1.2.10 Serial Control Ports (SPI™ or I2C™ Standards)
      • 1.2.11 SDRAM Controller
      • 1.2.12 Flash Controller
      • 1.2.13 DMA Controller
      • 1.2.14 Timers
      • 1.2.15 Clock Manager and PLL
      • 1.2.16 Programmable Interrupt Controller
  • Chapter 2: Operational Modes
    • 2.1 Overview
    • 2.2 Operational Mode Selection
    • 2.3 Slave Boot Procedures
      • 2.3.1 Host Controlled Master Boot
        • 2.3.1.1 Performing a Host Controlled Master Boot (HCMB)
          • 2.3.1.1.1 Host Controlled Master Boot (HCMB) Procedure
      • 2.3.2 Slave Boot
        • 2.3.2.1 Performing a Slave Boot
          • 2.3.2.1.1 Slave Boot Procedure
      • 2.3.3 Boot Messages
        • 2.3.3.1 Slave Boot
        • 2.3.3.2 Host-Controlled Master Boot from Parallel ROM
        • 2.3.3.3 Host-Controlled Master Boot from I2C ROM
        • 2.3.3.4 Host-Controlled Master Boot from SPI ROM
        • 2.3.3.5 Soft Reset
        • 2.3.3.6 Messages Read from CS4953xx
    • 2.4 Master Boot Procedure
    • 2.5 Softboot
      • 2.5.1 Softboot Messaging
      • 2.5.2 Softboot Procedure
        • 2.5.2.1 Softboot Procedure
        • 2.5.2.2 Softboot Example
        • 2.5.2.3 Softboot Example Steps
  • Chapter 3: Serial Control Port
    • 3.1 Overview
    • 3.2 Serial Control Port Configuration
    • 3.3 I2C Port
      • 3.3.1 I2C System Bus Description
      • 3.3.2 I2C Bus Dynamics
      • 3.3.3 I2C Messaging
        • 3.3.3.1 SCP1_BSY Behavior
        • 3.3.3.2 Performing a Serial I2C Write
        • 3.3.3.3 I2C Write Protocol
        • 3.3.3.4 Performing a Serial I2C Read
        • 3.3.3.5 I2C Read Procedure
        • 3.3.3.6 SCP1_IRQ Behavior
    • 3.4 SPI Port
      • 3.4.1 SPI System Bus Description
      • 3.4.2 SPI Bus Dynamics
        • 3.4.2.1 SCP1_BSY Behavior
      • 3.4.3 SPI Messaging
        • 3.4.3.1 Performing a Serial SPI Write
        • 3.4.3.2 SPI Write Protocol
        • 3.4.3.3 Performing a Serial SPI Read
        • 3.4.3.4 SPI Read Protocol
        • 3.4.3.5 SCP1_IRQ Behavior
  • Chapter 4: Parallel Control Port
    • 4.1 Parallel Control Availability
  • Chapter 5: Digital Audio Input Interface
    • 5.1 Digital Audio Input Port Description
      • 5.1.1 DAI Pin Description
      • 5.1.2 Supported DAI Functional Blocks
      • 5.1.3 BDI Port
      • 5.1.4 Digital Audio Formats
        • 5.1.4.1 I2S Format
        • 5.1.4.2 Left-Justified Format
    • 5.2 DAI Hardware Configuration
      • 5.2.1 DAI Hardware Naming Convention
  • Chapter 6: Direct Stream Data (DSD) Input Interface
    • 6.1 Description of Digital Audio Input Port when Configured for DSD Input
      • 6.1.1 DSD Pin Description
      • 6.1.2 Supported DSD Functional Blocks
  • Chapter 7: Digital Audio Output Interface
    • 7.1 Digital Audio Output Port Description
      • 7.1.1 DAO Pin Description
      • 7.1.2 Supported DAO Functional Blocks
      • 7.1.3 DAO Interface Formats
        • 7.1.3.1 I2S Format
        • 7.1.3.2 Left-Justified Format
        • 7.1.3.3 One-line Data Mode Format (Multichannel)
      • 7.1.4 DAO Hardware Configuration
      • 7.1.5 S/PDIF Transmitter
  • Chapter 8: External Memory Interfaces
    • 8.1 SDRAM Controller
    • 8.2 Flash Memory Controller
      • 8.2.1 Flash Controller Interface
    • 8.3 SDRAM/Flash Controller Interface
      • 8.3.1 SDRAM/Flash Interface Signals
      • 8.3.2 Configuring SDRAM/Flash Parameters
  • Chapter 9: System Integration
    • 9.1 Typical Connection Diagrams
    • 9.2 Pin Description
      • 9.2.1 Power and Ground
        • 9.2.1.1 Power
        • 9.2.1.2 Ground
        • 9.2.1.3 Decoupling
      • 9.2.2 PLL Filter
        • 9.2.2.1 Analog Power Conditioning
      • 9.2.3 PLL
    • 9.3 Clocking
    • 9.4 Control
      • 9.4.1 Operational Mode
    • 9.5 144-Pin LQFP Pin Assigments
    • 9.6 128-Pin LQFP Pin Assigments
    • 9.7 Pin Assignments
    • Revision History