Document Outline

• Table of Contents
• List of Figures
• List of Tables
• 1. General Description
  • 1.1 Digital Filter Features
  • 1.2 Integrated Peripheral Features
  • 1.3 System Level Features
  • 1.4 Configuration Interface
• 2. Characteristics and Specifications
  • Specified Operating Conditions
  • Absolute Maximum Ratings
  • Thermal Characteristics
  • Digital Characteristics
  • Power Consumption
  • Switching Characteristics
• 3. System Design with CS5376A
  • 3.1 Power Supplies
  • 3.2 Reset Control
  • 3.3 Clock Generation
  • 3.4 Synchronization
  • 3.5 System Configuration
  • 3.6 Digital Filter Operation
  • 3.7 Data Collection
  • 3.8 Integrated peripherals
• 4. Power Supplies
  • 4.1 Pin Descriptions
  • 4.2 Bypass Capacitors
  • 4.3 Power Consumption
• 5. Reset Control
  • 5.1 Pin Descriptions
  • 5.2 Reset Self-Tests
  • 5.3 Boot Configurations
• 6. Clock Generation
  • 6.1 Pin Description
  • 6.2 Synchronous Clocking
  • 6.3 Master Clock Jitter and Skew
• 7. Synchronization
  • 7.1 Pin Description
  • 7.2 MSYNC Generation
  • 7.3 Digital Filter Synchronization
  • 7.4 Modulator Synchronization
  • 7.5 Test Bit Stream Synchronization
• 8. Configuration By EEPROM
  • 8.1 Pin Descriptions
  • 8.2 EEPROM Hardware Interface
  • 8.3 EEPROM Organization
  • 8.4 EEPROM Configuration Commands
  • 8.5 Example EEPROM Configuration
• 9. Configuration By Microcontroller
  • 9.1 Pin Descriptions
  • 9.2 Microcontroller Hardware Interface
  • 9.3 Microcontroller Serial Transactions
  • 9.4 Microcontroller Configuration Commands
  • 9.5 Example Microcontroller Configuration
• 10. Modulator Interface
  • 10.1 Pin Descriptions
  • 10.2 Modulator Clock Generation
  • 10.3 Modulator Synchronization
  • 10.4 Modulator Data Inputs
  • 10.5 Modulator Flag Inputs
• 11. Digital Filter Initialization
  • 11.1 Filter Coefficient Selection
  • 11.2 Filter Configuration Options
• 12. SINC Filter
  • 12.1 SINC1 Filter
  • 12.2 SINC2 Filter
  • 12.3 SINC3 Filter
  • 12.4 SINC Filter Synchronization
• 13. FIR Filter
  • 13.1 FIR1 Filter
  • 13.2 FIR2 Filter
  • 13.3 On-Chip FIR Coefficients
  • 13.4 Programmable FIR Coefficients
  • 13.5 FIR Filter Synchronization
• 14. IIR Filter
  • 14.1 IIR Architecture
  • 14.2 IIR1 Filter
  • 14.3 IIR2 Filter
  • 14.4 IIR3 Filter
  • 14.5 On-Chip IIR Coefficients
  • 14.6 Programmable IIR Coefficients
  • 14.7 IIR Filter Synchronization
• 15. Gain and Offset Correction
  • 15.1 Gain Correction
  • 15.2 Offset Correction
  • 15.3 Offset Calibration
• 16. Serial Data Port
  • 16.1 Pin Descriptions
  • 16.2 SD Port Data Format
  • 16.3 SD Port Transactions
• 17. Test Bit Stream Generator
  • 17.1 Pin Descriptions
  • 17.2 TBS Architecture
  • 17.3 TBS Configuration
  • 17.4 TBS Data Source
  • 17.5 TBS Sine Wave Output
  • 17.6 TBS Loopback Testing
  • 17.7 TBS Synchronization
• 18. Time Break Controller
  • 18.1 Pin Description
  • 18.2 Time Break Operation
  • 18.3 Time Break Delay
• 19. General Purpose I/O
  • 19.1 Pin Descriptions
  • 19.2 GPIO Architecture
  • 19.3 GPIO Registers
  • 19.4 GPIO Input Mode
  • 19.5 GPIO Output Mode
• 20. Serial Peripheral Interface 2
  • 20.1 Pin Descriptions
  • 20.2 SPI 2 Architecture
  • 20.3 SPI 2 Registers
  • 20.4 SPI 2 Transactions
• 21. Boundary Scan JTAG
  • 21.1 Pin Descriptions
  • 21.2 JTAG Architecture
• 22. Device Revision History
  • 22.1 Changes from CS5376 rev A to CS5376 rev B
  • 22.2 Changes from CS5376 rev B to CS5376A rev A
• 23. Register Summary
  • 23.1 SPI 1 Registers
  • 23.2 Digital Filter Registers
• 24. Pin Descriptions
• 25. Package Dimensions
• 26. Ordering Information
• 27. Environmental, Manufacturing, & Handling Information
• 28. Revision History