Rockwell Automation 1746-FIO4V SLC 500 Fast Analog I/O/ User Manual - Manual (Page 53)

Publication 1746-UM009B-EN-P - September 2007
Write Ladder Logic 53
Ladder Logic
We present two examples. The first runs on any SLC 500 processor.
The second uses the scaling instruction available on SLC 5/02 (and
later) processors.
In the first example, the analog input value is checked against the
minimum and maximum input limits. B3:0/0 is the in-range flag bit.
If the input is out of range, the in-range flag bit is reset and the output
is set to its minimum or maximum limit. If the input is in range, the
output value is determined by scaling the input.
Follow these steps to scale an analog input for this example.
1. Multiply the input by the scaled range
Scale range = (scaled max – scaled min) = 3276 – 0 = 3276
2. Divide the 32 bit result by the input range
Input range = (input max – input min) = 2047 – 409 = 1638
3. Add the offset value (in this case negative) = –818
Move the final value to the analog output channel 0.
In this example, the multiply operation generates an overflow bit and
minor error flag whenever the result exceeds 16 bits. Since the divide
operation uses a 32-bit result in the math register, the overflow is no
problem. The minor error flag has to be cleared before the end of the
program scan to avoid a system error.
Refer to the ladder program on the next page.