Overflow/underflow, 8b/10b decoder, Bit slider – Achronix Speedster22i SerDes User Manual
Page 31: Table 3: shift limit

Overflow/Underflow
If the difference between the write and read counters is greater than fifo_full, then the
overflow signal is asserted. If the difference between the write and read counters is less than
fifo_empty, then the underflow signal is asserted.
8b/10b Decoder
The 8b/10b decoder generates 8-bit code groups and 1-bit control from 10-bit encoded
(received) data. It uses the code group mapping specified in IEEE 802.3 clause 36. If the fabric
interface is a 16-bit data path, then two 8b/10b decoders are cascaded to produce 16-bit data
to the fabric. The decoder handles various error conditions. All error conditions are reported
per each byte lane.
The 8b/10b code allows 12 special (K) characters, but most standards generally support fewer
K characters and need the reserved K characters to be declared as code errors. So register
programming is possible to pre-configure 11 characters that can be declared as invalid for
deciding code error if seen in the receive data stream, and assuming that at least one special
character will be needed.
Any 10-bit code word that is not present in Tables 36-1, 36-2 of the IEEE 802.3-2005
specification shall be considered as invalid code word. In addition, 11 code words
corresponding to the K characters can be included (programmable) to be flagged as invalid
code words. If the 10-bit code word is present in Tables 36-1 or 36-2, but corresponds to the
wrong column (per current running disparity calculation), the wrong column indication is
asserted. Disparity and code errors are not mutually exclusive; however code error and
wrong column are mutually exclusive.
For XAUI and Gigabit Ethernet, a code error or disparity error will cause the error indication
to be propagated downstream. For PCIe, if a code error and disparity error are detected on
the same byte, the pipe_RXstatus is encoded to indicate a code error.
Bit Slider
The bit slider is a barrel shifter that can be used to control bit-wise skew from the fabric. This
feature can be used to implement any user specific algorithm for lane alignment and de-
skew. It can also be used in conjunction with the symbol slip mode of the de-skew FIFO to
attain a wide range of de-skew. The symbol slip mode can be used for coarse alignment (with
1 or 2 symbols shifting per request) and the bit slider can be used for finer alignment within a
symbol. The barrel shifter width is limits are shown in “Table 3: Shift Limit” below.
Table 3: Shift Limit
Data Path width
Shift limit
20
83
16
79
10
73
8
71
The MSBs is shifted to the location of the LSBs and the LSBs are discarded. There is a 6-bit
select control from the fabric to pick the active data to be driven to the fabric. For example, in
UG028, July 1, 2014
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