Achronix Speedster22i SerDes - Manual (Page 92)

Related modifications are listed below:
Simple_serdes_design_efifo_wrapper iSerDes
(
// =============================
// Lane 0
// **********************
// Inputs to SerDes
// **********************
.. .. ..
.. .. ..
// **********************
// Outputs from SerDes
// **********************
// Data received from SerDes
.. .. ..
.. .. ..
// Clocks from SerDes
.ch0_o_TX_data_clk (ln0_TX_clk),
.ch0_o_RX_data_clk (ln0_RX_clk_unused),
// okay to keep floating as well.
);
• Modification to the code related to the generation of divide_by_2 clock signals that are
used for debug purpose:
// ln0_TX_clk_div2 and ln0_RX_clk_div2 have been defined as primary outputs.
//
// Generation of divide-by-2 clock, based on TX-clk generated by SerDes
always @ (posedge ln0_TX_clk or negedge ln0_rst_n_TX)
begin
if (ln0_rst_n_TX == 1'b0)
ln0_TXclk_div2 <= 1'b0;
else
ln0_TXclk_div2 <= ~ln0_TXclk_div2;
end
// ************************************************************************
// ******* We comment out the divide_by_2 clock for ln0_RX_clk
// Generation of divide-by-2 clock, based on RX-clk generated by SerDes
// always @ (posedge ln0_RXclk or negedge ln0_rst_n_RX)
// begin
// if (ln0_rst_n_RX == 1'b0)
// ln0_RXclk_div2 <= 1'b0;
// else
// ln0_RXclk_div2 <= ~ln0_RXclk_div2;
// end
// **** Commented out
// ************************************************************************
92 UG028, July 1, 2014