Achronix Speedster22i SerDes - Manual (Page 4)

RX PCS Settings ............................................................................................................................................. 64
RX PCS Symbol Alignment ............................................................................................................................. 66
TX PCS Settings ............................................................................................................................................. 68
Section on Manually Overriding PMA/PCS Register Values: ......................................................................... 69
Generation of Wrapper Files: .......................................................................................................................... 70
Files Generated by ACE-GUI ........................................................................................................... 71
Integration of SerDes Wrapper in a Design ...................................................................................... 72
Design and Wrapper Files .............................................................................................................................. 72
Dynamically Changing the SerDes Register Values....................................................................................... 75
Using sBus module to enable internal loopback ............................................................................................. 75
Placement of SerDes ....................................................................................................................... 77
Timing Constraints .......................................................................................................................................... 78
Test bench Setup for Simulation ..................................................................................................................... 79
Design Guidelines ............................................................................................................................ 80
Reset Sequence ............................................................................................................................................. 80
SerDes Placement and Clocking Limitations .................................................................................................. 80
Wide Bus ......................................................................................................................................................... 86
Design Tips ..................................................................................................................................................... 87
Variants of the Simple Design .......................................................................................................... 88
Design Bypassing PCS: .................................................................................................................................. 93
Bypassing PCS by Manually Overriding Corresponding Register .................................................................. 95
Dynamic Read/Write of SerDes Registers via SBUS .................................... 98
Overview .......................................................................................................................................... 98
Alternatives for using SBUS interface for SerDes register access: ................................................................ 98
ACX_SERDES_SBUS_IF Module ................................................................................................... 99
The Ports of ACX_SERDES_SBUS_IF Module: .......................................................................................... 100
Loopback Modes ........................................................................................................................................... 102
SerDes Registers ........................................................................................... 103
Electrical Specifications ............................................................................... 104
Operating Conditions ..................................................................................................................... 104
Transmitter .................................................................................................................................... 105
Receiver ........................................................................................................................................ 108
Eye Diagram ................................................................................................................................................. 110
Reference Clock ............................................................................................................................ 112
Jitter Specification ......................................................................................................................................... 112
Revision History ............................................................................................ 113
4 UG028, July 1, 2014