List of Figures
Figure 1: Location of SerDes Lanes ...................................................................................................................................... 11
Figure 2: SerDes Architecture................................................................................................................................................ 12
Figure 3: PMA Architecture .................................................................................................................................................. 13
Figure 4: Synthesizer Architecture ....................................................................................................................................... 14
Figure 5: Receiver Architecture ............................................................................................................................................. 15
Figure 6: PCS Transmitter Block Overview ......................................................................................................................... 16
Figure 7: 20 bit Order Reversal ............................................................................................................................................. 17
Figure 8: 20-bit Byte Order Swap/Reversal ......................................................................................................................... 17
Figure 9: Polarity Inversion (16-bit Word) .......................................................................................................................... 18
Figure 10: Bit Order Inversion (16-bit Word) ...................................................................................................................... 18
Figure 11: Word Order Inversion (16-bit Word) ................................................................................................................. 19
Figure 12: 8b/10b Encoding Process ..................................................................................................................................... 21
Figure 13: PCS Receive Block Overview .............................................................................................................................. 22
Figure 14: Operating principle of deskew technique ......................................................................................................... 25
Figure 15: EFIFO SKP Addition/Removal ........................................................................................................................... 29
Figure 16: EFIFO SKP Addition/Removal: PCIE, GigE (802.3) and XAUI (802.3) ......................................................... 30
Figure 17: SerDes RX and TX clocks ..................................................................................................................................... 36
Figure 18: PMA Loopback Modes ........................................................................................................................................ 39
Figure 19: Looback modes ..................................................................................................................................................... 39
Figure 20 Worst-case latency across PMA and PCS (in terms of clock-cycles) .............................................................. 44
Figure 21: Opening IP Configuration Perspective .............................................................................................................. 50
Figure 22: New IP Configuration Window ......................................................................................................................... 51
Figure 23: New IP Configuration Window- Overview Page ............................................................................................ 52
Figure 24: Outline Window ................................................................................................................................................... 52
Figure 25: IP Diagran Window ............................................................................................................................................. 52
Figure 26: New IP Configuration Window – Populating Overview Page ...................................................................... 53
Figure 27: Issues with Setting TX/RX data rate and reference clock frequency ............................................................. 56
Figure 28: Unavailable Fields ................................................................................................................................................ 57
Figure 29: PMA Settings Window – First page ................................................................................................................... 58
Figure 30: Outline Window, When Lane-Specific PMA Settings are Enabled ............................................................... 59
Figure 31: PCS Settings Window – First page ..................................................................................................................... 63
Figure 32: PCS Settings for Receiver – Default Settings .................................................................................................... 64
Figure 33: PCS Settings for Receiver – Symbol Alignment ............................................................................................... 66
Figure 34: PCS Settings for Receiver – TX PCS Settings .................................................................................................... 68
Figure 35: Generating the Wrapper Files ............................................................................................................................. 70
Figure 36: TCL console message upon successful generation of wrapper files .............................................................. 71
Figure 37: Clock Region View ............................................................................................................................................... 82
Figure 38: Physical assignment of SerDes Lanes ................................................................................................................ 84
Figure 39: SerDes Placement Guidelines ............................................................................................................................. 85
Figure 40: PCS Settings for Receiver – Configurations for Decoder and Elastic FIFO .................................................. 91
Figure 41: Disabling PCS from ACE GUI ............................................................................................................................ 95
Figure 42: Modifying Register Settings from ACE GUI .................................................................................................... 96
Figure 43: Changing Value of Register 17A to bypass PCS block .................................................................................... 97
Figure 44: Disabling PCS Decoder (default ACE Setting) ................................................................................................. 99
Figure 45: Connections for ACX_SERDES_LOOPBACK_CTRL .................................................................................... 101
Figure 46: Receiver (RX) Eye Diagram Specification ....................................................................................................... 110
UG028, July 1, 2014
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