Achronix Speedster22i SerDes - Manual (Page 93)

Modification – 3 (placement and timing constraints): Since there is only one divide-by-two
clock in this derivative of the design, we can remove the placement for ln0_RXclk_div2 from
ace_placement.pdc.
Contents of the ace_constraints.sdc file can be copied from the ACE generated .sdc file except
for the constraints related to the user-defined clocks (such as, reference clocks and snapshot
clocks).
Design Bypassing PCS:
There are two modes for bypassing a PCS:
1. PCS Enabled mode: In this mode, PCS is not disabled, but all of the PCS modules are
disabled. In other words, data (transmit and receive) will travel through the PCS components
while bypassing them, as shown in “Figure 6: PCS Transmitter Block Overview”.
2. PCS Bypassed mode: In this mode, the PCS block is bypassed on both transmit and
receive datapaths. This is shown in “Figure 6: - PCS Transmitter Block Overview”.
Note: While creating the baseline design (simple_serdes_design), the PCS has been kept
enabled while bypassing some PCS modules, such as EFIFO and deskew modules.
“Table 9: Latency across the PCS blocks” presents the latency that the data-path experiences
for each of the above two modes:
With respect to the simple baseline design (simple_serdes_design) where some of the PCS
modules are used, this derivative of the design will bypass PCS module individually (Mode-
1 above) or will completely bypass the PCS block (Mode-2 above). This derivative of the
baseline design is called simple_serdes_design_pcs_bypass. For this derivative, this section
presents the derivatives with respect to the design flow used for creating the baseline design.
Specifications for this derivative are shown below.
Design name : simple_serdes_design_pcs_bypass
Objective : Send data to SerDes and read-back using loopback.
Data rate : 10.3125 Gbps
Standard : Generic
Number of lane : 1
Placement (lane to be used): Bottom-lane# 8
Ref. clock : 161.138125 Mhz
Data width : 20 (Wrapper will use wide-bus to make data 40-bit wide)
PCS blocks used : None
Mode – a: PCS modules are disabled
Mode – b: PCS is disabled as a block.
No comma character required for transmit data since we are not using symbol alignment or
deskew blocks.
Overview of the changes: Compared to the design flow used for the baseline design, the
following changes are made for simple_serdes_design_pcs_bypass:
1. Change in using ACE GUI during wrapper generation.
2. Change in RTL code.
Note: There will be no change required for placement-constraint (ace_placement.pdc) and
timing-constraint (ace_constraint.sdc) when compared to the files used for the baseline
design.
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