Achronix Speedster22i SerDes - Manual (Page 37)

Although each lane has its own clock output pins to the fabric, with lane bonding these are
all just route-throughs of the master clock: regardless of which clock output pins are used,
only one clock net is routed inside the fabric. This is an important feature of Lane Bonding,
because the FPGA fabric can only accommodate a limited number of distinct clocks. Lane
Bonding divides the number of distinct clocks inside the core by the size of the group. Note
that Lane Bonding is only possible when all lanes share the same reference clock, both at the
near end and at the far end.
An additional method of reducing the number of distinct clocks is to use the Elastic FIFO.
That FIFO can be used to convert data from the RX domain to the TX domain, thus reducing
the number of distinct clocks by half. In Elastic FIFO mode, the RX clock output to the fabric
is just a route-through of the TX clock: either clock pin can be used, and only a single net will
be routed inside the fabric. See Section “Elastic FIFO” for details of Elastic Buffer operation.
Elastic FIFO mode and Lane Bonding mode can be combined, reducing the number of clocks
to one for the entire bonded group.
As mentioned above, a 10Gbps data rate results in a 500MHz clock output to the user design
(or 625MHz for 16 bit words). For most designs, timing closure at such high clock speeds is
unrealistic. Because of that, the SerDes macro includes a “Wide Bus” feature, which divides
the clock frequency by two and doubles the data width. When the Wide Bus feature is
enabled, the TX and RX clock outputs from the macro to the user design are the divided
clocks, and the user design does not need to deal with the faster clock at all. However,
because the Wide Bus is implemented in the fabric, both the fast and divided clocks do occur
in the fabric, counting towards the maximum number of distinct clocks. The Wide Bus
feature can be combined with Lane Bonding and Elastic FIFO modes. See the Section “Design
Guidelines” for specifics on the number of distinct clocks that the fabric can support, and for
details of the Wide Bus feature.
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