Achronix Speedster22i SerDes - Manual (Page 35)

The 128b/130b encoder is disabled on power up, and enabled when the rate bits coming from
the MAC are configured to 2’b10. The PCS layer support for PCIe gen3 also includes glue
logic to switch the PMA data width to 16-bit mode and programming final rate bits for PCIe
gen3 operation. “Table 5: PIPE Interface Paramaters” shows various supported combinations
of clocking speeds and data-widths.
Table 5: PIPE Interface Paramaters
PCIe Mode PCLK PMA Data Width
2.5 Gbps Gen1 250 Mhz 10 bits
2.5 Gbps Gen1 125 Mhz 20 bits
5.0 Gbps Gen2 500 Mhz 10 bits
5.0 Gbps Gen2 250 Mhz 20 bits
8.0 Gbps Gen3 500 Mhz 16 bits
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