Achronix Speedster22i SerDes - Manual (Page 63)

Table 16: TX PMA PLL Settings
Entry field Purpose Available Options Choice made
TX PPM
Configure the PPM difference
between reference clock and
divided down PLL clock to
assert PLL lock status signal
Text-box entry. The user
may enter any value.
1000 (Default)
Section on PCS Settings:
The user can reach the PCS Settings section by browsing through the pages related to the
PMA Settings section. Alternatively, the user may reach this section by clicking the PCS
Settings link on the Overview window. The pages belonging to the PCS Settings section
allow the user to define the PCS-specific settings. Different components of the SerDes PCS
block are explained in Chapter – “PCS Blocks in Transmitter (TX) Data path”.
The first page of PCS Settings section is shown in “Figure 31: PCS Settings Window – First
page”. This page allows the users to choos lane specific PCS properties for a multi-lane
design. For the current single-lane design, these options are not relevant.
Figure 31: PCS Settings Window – First page
Clicking Next button on the first page will bring up the page for RX PCS Settings. This page
with default settings are shown in “Figure 32: PCS Settings for Receiver – Default Settings”. It
is observed in “Figure 32: PCS Settings for Receiver – Default Settings” that some entry fields
are disabled based on user-choices. For instance, the fields related to Elastic FIFO (EFIFO)
and Transition Density Checker (TDC) are not available for user-entry/user-choices since
EFIFO and TDC are disabled by default.
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