Achronix Speedster22i SerDes - Manual (Page 87)

Design Tips
Timing report of a routed design: When a design passes through the place-and-route tool,
please make sure that there is no setup- and/or hold-time violation for the routed design.
Section-4 of the ACE User Document provides a detailed description of checking the timing
reports generated by ACE.
Bringing up debug/status signals from the top-level RTL: To facilitate debugging of a design,
we can bring up the SerDes status signals to on-board LED’s and/or SMA/SMP connectors.
“Table 20: Signals passed between the SerDes Instance and the Top-Level module” provides
a list of debugging signals that we use as primary outputs from the top-level RTL:
simple_serdes_design_top.v.
Note: These signals can be used for other purposes as well. For example, ln0_pma_TX_ready
signal can be used to enable the data-generation and transmission to SerDes.
Observing the clocks from SerDes: It is a good idea to observe the RX and TX clock signals
that are generated by SerDes. The user may not directly connect these signals (ln0_RX_clk
and ln0_TX_clk) to SMA connectors. An alternative way of observing these signals is to
generate a signal (in the fabric) based on these clocks and connect them to SMA connectors.
The following code snippet from simple_serdes_design_top.v shows two clock signals that
are generated in the fabric. The frequency of these generated signals are half of that for the
TX and the RX clock frequencies.
// ln0_TX_clk_div2 and ln0_RX_clk_div2 have been defined as primary outputs.
//
// Generation of divide-by-2 clock, based on TX-clk generated by SerDes
always @ (posedge ln0_TX_clk or negedge ln0_rst_n_TX)
begin
if (ln0_rst_n_TX == 1'b0)
ln0_TXclk_div2 <= 1'b0;
else
ln0_TXclk_div2 <= ~ln0_TXclk_div2;
end
// Generation of divide-by-2 clock, based on RX-clk generated by SerDes
always @ (posedge ln0_RXclk or negedge ln0_rst_n_RX)
begin
if (ln0_rst_n_RX == 1'b0)
ln0_RXclk_div2 <= 1'b0;
else
ln0_RXclk_div2 <= ~ln0_RXclk_div2;
end
For observation, we need to connect these signals to SMA connectors, which require the
addition of the following two lines in src/constraints/ace_placement.pdc file:
#div2 version of SerDes RX and TX clocks
set_placement -batch -fixed {p:ln0_TXclk_div2} {SMA Pin in Development Board}
set_placement -batch -fixed {p:ln0_RXclk_div2} {SMA Pin in Development Board}
The frequency of RX and TX clock does not depend on the reference clock that we are using,
which is 156.25 MHz in our sample design. Rather, the frequency of the clocks generated by
SerDes depends on the data-rate and data-width. This frequency is determined by ACE GUI
while generating the wrapper file.
UG028, July 1, 2014 87