Achronix Speedster22i SerDes - Manual (Page 71)

If the files are successfully generated, the user will find the corresponding message on the
TCL sub-window, as shown in “ Figure 36: TCL console message upon successful generation
of wrapper files”.
Figure 36: TCL console message upon successful generation of wrapper files
Files Generated by ACE-GUI
Based on the directory structure and the file names that have been chosen (“Figure 35:
Generating the Wrapper Files”), there will be up to five files in simple_serdes_design/src/ace
folder:
• simple_serdes_design_wrapper.v: This file contains the RTL generated by ACE GUI. The
top level module for this wrapper is simple_serdes_design_wrapper. This module will be
instantiated in top level design module: simple_serdes_design.v file.
• simple_serdes_design_wrapper.vhd: If the VHDL file generation has been chosen.
• simple_serdes_design_wrapper.sdc: This file will provide the timing constraints for the
SerDes PLL clocks. This file further identifies the related and unrelated clocks.
• simple_serdes_design_wrapper.pdc: This file will provide the placement of the SerDes
lanes, based on the lane-positioning chosen in the Overview page (“Figure 26: New IP
Configuration Window – Populating Overview Page”).
• simple_serdes_design_registers.txt: This file will provide the values for all PCS and PMA
registers, based on the choices made in ACE GUI.
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